Today, Jon populated channel 2 on our two development boards. We replicated the original component values that were specified in the initial channel 1 design. We hope by making this choice that software design will be simplified as hardware will be uniform.
Today, I continued my effort to implement my Digital IIR Filter on the micro controller. In my last post I documented the development cycle of a simulation I ran. The actual process of implementing the subvi on the micro-controller was difficult.
The problem I ran into was trying to verify that the ADC values were in fact being sent to an array. It's critical that the values be stored in some dataset because the digital filter operates on past values. I discovered that the JTAG interface does not send array contents back so the VI front panel was not updating. A quick hack suggested by Cevin was to use the OLED to display array contents. I had the screen output the i-1 item in the array so that it was always displaying the previous updated array item. In this way, I was able to verify that the data was being stored. After concluding that the data was stored I proceeded to implement the DC Filter as a subvi. Everything worked out of the box and the program now shows a DC offset from output of ADC.
In the future, I'd like to link the ADC array output back to the computer so I can debug more thoroughly and plot the ADC output.
Goals for next week:
1. Fully operational TIA section. I will be going back and increasing the feedback resistor to bring the signal closer to 5 volts. I'll likely need to performing a stability analysis and perform some form of compensation to decrease the oscillation. I will provide an update later this week on my efforts.
2. Improve performance of POX Software Controller. Right now I've split many of the components into SubVI's. Now that the program can determine DC bias I will be creating a software solution to modify DC bias dynamically from this input. For instance, today in lab I observed that the output from the DC Tracker was 2240 corresponding to analog voltage of around 2.69v. In the future I want to be able to push this DC offset to 2.5v so I will have to dynamically modify the DAC value for DC subtraction.
I will also this week be integrating this with the ability to increase gain in the PGA stage. I had implemented the PGA as a SubVI but this isn't working. I think labview doesn't like elemental IO pins in subvi so I need to figure that out. So goal this week is to be able to give a PGA gain of 200 and keep DC offset at steady 2.5v auto.
3. Jon is work on testing the channel 2 and fixing all problems.
4. Megan is running a simulation in LabVIEW. The simulation will entail a mock gain session on a sinusoid with a random AC amplitude. The program will be adaptive and try to take full scale of the ADC. Therefore, the program will required some conditional logic to determine if PGA is possible if it won't saturate. The program will also have ability to add smaller AC bias from increasing brightness of LED.
This is really just a simulation but the reasoning will serve how we make our adaptive process to modify parameters to get full scale performance from ADC.
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